[FFmpeg-cvslog] r12410 - in trunk: libavcodec/avcodec.h libavcodec/dsputil.h libavcodec/mpegvideo_enc.c libavcodec/ppc/mpegvideo_altivec.c libavformat/mov.c libavformat/nutenc.c libavutil/aes.h libavutil/avutil.h libavutil/bswap.h libavutil/common.h libavutil/mem.c libpostproc/postprocess.h

[Benoit Fouet]

Hi,

diego wrote:
> Modified: trunk/libavcodec/dsputil.h
> ==============================================================================
> --- trunk/libavcodec/dsputil.h	(original)
> +++ trunk/libavcodec/dsputil.h	Mon Mar 10 19:42:09 2008
> @@ -93,11 +93,14 @@ void ff_gmc_c(uint8_t *dst, uint8_t *src
>                int dxx, int dxy, int dyx, int dyy, int shift, int r, int width, int height);
>  
>  /* minimum alignment rules ;)
> -if u notice errors in the align stuff, need more alignment for some asm code for some cpu
> -or need to use a function with less aligned data then send a mail to the ffmpeg-dev list, ...
> +If you notice errors in the align stuff, need more alignment for some ASM code
> +for some CPU or need to use a function with less aligned data then send a mail
> +to the ffmpeg-devel mailing list, ...
>  
> -!warning these alignments might not match reallity, (missing attribute((align)) stuff somewhere possible)
> -i (michael) didnt check them, these are just the alignents which i think could be reached easily ...
> +!warning These alignments might not match reality, (missing attribute((align))
> +stuff somewhere possible).
> +I (Michael) did not check them, these are just the alignments which i think
>   

s/i/I/
or was it on purpose ?

> Modified: trunk/libavutil/mem.c
> ==============================================================================
> --- trunk/libavutil/mem.c	(original)
> +++ trunk/libavutil/mem.c	Mon Mar 10 19:42:09 2008
> @@ -69,10 +69,10 @@ void *av_malloc(unsigned int size)
>         But I don't want to code such logic here!
>       */
>       /* Why 16?
> -        because some cpus need alignment, for example SSE2 on P4, & most RISC cpus
> +        Because some CPUs need alignment, for example SSE2 on P4, & most RISC CPUs
>          it will just trigger an exception and the unaligned load will be done in the
>          exception handler or it will just segfault (SSE2 on P4)
> -        Why not larger? because i didnt see a difference in benchmarks ...
> +        Why not larger? because i did not see a difference in benchmarks ...
>   

ditto

-- 
Benoit Fouet
Purple Labs S.A.
www.purplelabs.com