[FFmpeg-devel] [PATCH] avutil/mips: Avoid instruction exception caused by gssqc1/gslqc1.

[Shiyou Yin]

>Why is "block" not aligned? Does the code for other architectures also use unaligned instructions for
>these?

Thank you for reminding me. After checking the struct H264SliceContext and function call process, 'block' is find out as 16-bit aligned.
There are some refines in this patch, I will upload them in a new patch and only keep the following changes in this patch(V2).

>> diff --git a/libavcodec/mips/simple_idct_mmi.c b/libavcodec/mips/simple_idct_mmi.c
>> index 7f4bb74..f54f9ea 100644
>> --- a/libavcodec/mips/simple_idct_mmi.c
>> +++ b/libavcodec/mips/simple_idct_mmi.c
>> @@ -39,7 +39,7 @@
>> #define COL_SHIFT 20
>> #define DC_SHIFT 3
>>
>> -DECLARE_ALIGNED(8, const int16_t, W_arr)[46] = {
>> +DECLARE_ALIGNED(16, const int16_t, W_arr)[46] = {
>>     W4,  W2,  W4,  W6,
>>     W1,  W3,  W5,  W7,
>>     W4,  W6, -W4, -W2,
>> diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
>> index 05f6b31..bfa6d8b 100644
>> --- a/libavutil/mips/mmiutils.h
>> +++ b/libavutil/mips/mmiutils.h
>> @@ -205,7 +205,7 @@
>>  * backup register
>>  */
>> #define BACKUP_REG \
>> -  double temp_backup_reg[8];                                    \
>> +  double __attribute__ ((aligned (16))) temp_backup_reg[8];     \
>>   if (_MIPS_SIM == _ABI64)                                      \
>>     __asm__ volatile (                                          \
>>       "gssqc1       $f25,      $f24,       0x00(%[temp])  \n\t" \
>> --
>> 2.1.0


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