[FFmpeg-devel] [PATCH v2] swscale: aarch64: Don't clobber callee-saved registers v8-v15
Martin Storsjö
martin at martin.st
Mon Apr 20 00:09:09 EEST 2020
---
If there would have been checkasm tests for these functions, it would
have been caught immediately.
Fixed one missed case (because the code used mixed upper/lower case
for register names, mixing v8 with V8, so I missed one with
search/replace, and as there's no dedicated checkasm test, it can only
be tested implicitly via other fate tests).
---
libswscale/aarch64/hscale.S | 20 ++++++++++----------
libswscale/aarch64/output.S | 6 +++---
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/libswscale/aarch64/hscale.S b/libswscale/aarch64/hscale.S
index ae73014a25..af55ffe2b7 100644
--- a/libswscale/aarch64/hscale.S
+++ b/libswscale/aarch64/hscale.S
@@ -46,20 +46,20 @@ function ff_hscale_8_to_15_neon, export=1
uxtl v4.8H, v4.8B // unpack part 1 to 16-bit
smlal v0.4S, v4.4H, v5.4H // v0 accumulates srcp[filterPos[0] + {0..3}] * filter[{0..3}]
smlal2 v0.4S, v4.8H, v5.8H // v0 accumulates srcp[filterPos[0] + {4..7}] * filter[{4..7}]
- ld1 {v8.8B}, [x0], #8 // srcp[filterPos[2] + {0..7}]
- ld1 {v9.8H}, [x13], #16 // load 8x16-bit at filter+2*filterSize
+ ld1 {v16.8B}, [x0], #8 // srcp[filterPos[2] + {0..7}]
+ ld1 {v17.8H}, [x13], #16 // load 8x16-bit at filter+2*filterSize
uxtl v6.8H, v6.8B // unpack part 2 to 16-bit
smlal v1.4S, v6.4H, v7.4H // v1 accumulates srcp[filterPos[1] + {0..3}] * filter[{0..3}]
- uxtl v8.8H, v8.8B // unpack part 3 to 16-bit
- smlal v2.4S, v8.4H, v9.4H // v2 accumulates srcp[filterPos[2] + {0..3}] * filter[{0..3}]
- smlal2 v2.4S, V8.8H, v9.8H // v2 accumulates srcp[filterPos[2] + {4..7}] * filter[{4..7}]
- ld1 {v10.8B}, [x11], #8 // srcp[filterPos[3] + {0..7}]
+ uxtl v16.8H, v16.8B // unpack part 3 to 16-bit
+ smlal v2.4S, v16.4H, v17.4H // v2 accumulates srcp[filterPos[2] + {0..3}] * filter[{0..3}]
+ smlal2 v2.4S, v16.8H, v17.8H // v2 accumulates srcp[filterPos[2] + {4..7}] * filter[{4..7}]
+ ld1 {v18.8B}, [x11], #8 // srcp[filterPos[3] + {0..7}]
smlal2 v1.4S, v6.8H, v7.8H // v1 accumulates srcp[filterPos[1] + {4..7}] * filter[{4..7}]
- ld1 {v11.8H}, [x4], #16 // load 8x16-bit at filter+3*filterSize
+ ld1 {v19.8H}, [x4], #16 // load 8x16-bit at filter+3*filterSize
subs w15, w15, #8 // j -= 8: processed 8/filterSize
- uxtl v10.8H, v10.8B // unpack part 4 to 16-bit
- smlal v3.4S, v10.4H, v11.4H // v3 accumulates srcp[filterPos[3] + {0..3}] * filter[{0..3}]
- smlal2 v3.4S, v10.8H, v11.8H // v3 accumulates srcp[filterPos[3] + {4..7}] * filter[{4..7}]
+ uxtl v18.8H, v18.8B // unpack part 4 to 16-bit
+ smlal v3.4S, v18.4H, v19.4H // v3 accumulates srcp[filterPos[3] + {0..3}] * filter[{0..3}]
+ smlal2 v3.4S, v18.8H, v19.8H // v3 accumulates srcp[filterPos[3] + {4..7}] * filter[{4..7}]
b.gt 2b // inner loop if filterSize not consumed completely
addp v0.4S, v0.4S, v0.4S // part0 horizontal pair adding
addp v1.4S, v1.4S, v1.4S // part1 horizontal pair adding
diff --git a/libswscale/aarch64/output.S b/libswscale/aarch64/output.S
index 25bf28b6e4..af71de6050 100644
--- a/libswscale/aarch64/output.S
+++ b/libswscale/aarch64/output.S
@@ -39,11 +39,11 @@ function ff_yuv2planeX_8_neon, export=1
ld1 {v5.8H}, [x11] // read 8x16-bit @ src[j ][i + {0..7}]: A,B,C,D,E,F,G,H
ld1 {v6.8H}, [x12] // read 8x16-bit @ src[j+1][i + {0..7}]: I,J,K,L,M,N,O,P
ld1r {v7.8H}, [x10], #2 // read 1x16-bit coeff X at filter[j ] and duplicate across lanes
- ld1r {v8.8H}, [x10], #2 // read 1x16-bit coeff Y at filter[j+1] and duplicate across lanes
+ ld1r {v16.8H}, [x10], #2 // read 1x16-bit coeff Y at filter[j+1] and duplicate across lanes
smlal v3.4S, v5.4H, v7.4H // val0 += {A,B,C,D} * X
smlal2 v4.4S, v5.8H, v7.8H // val1 += {E,F,G,H} * X
- smlal v3.4S, v6.4H, v8.4H // val0 += {I,J,K,L} * Y
- smlal2 v4.4S, v6.8H, v8.8H // val1 += {M,N,O,P} * Y
+ smlal v3.4S, v6.4H, v16.4H // val0 += {I,J,K,L} * Y
+ smlal2 v4.4S, v6.8H, v16.8H // val1 += {M,N,O,P} * Y
subs w8, w8, #2 // tmpfilterSize -= 2
b.gt 3b // loop until filterSize consumed
--
2.17.1
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