[FFmpeg-devel] [PATCH] lavc/vc1dsp: R-V V inv_trans
flow gg
hlefthleft at gmail.com
Mon Dec 4 10:48:56 EET 2023
> Probably missing VLENB checks.
Changed.
> You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add
> then shift, and by 17 with shift then add. You don't need multiplications.
Changed.
> Do you really need to splat? Can't .vx or .wx be used instead?
Okay, for example in ff_vc1_inv_trans_8x8_dc_rvv
+ vsetvli zero, t0, e8, m2, ta, ma
+ vwaddu.vx v4, v0, zero
+ vsetvli zero, t0, e16, m4, ta, ma
+ vadd.vx v4, v4, t2
- vsetvli zero, t0, e16, m4, ta, ma
- vmv.v.x v4, t2
- vsetvli zero, t0, e8, m2, ta, ma
- vwaddu.wv v4, v4, v0
But the speed has slowed down slightly on the c910, I'm not sure if I
should modify it.
splat | no splat
vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0 | 84.0
vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0 | 76.0
vc1dsp.vc1_inv_trans_4x8_dc_c: 150.0 | 150.0
vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5 | 84.5
vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0 | 129.0
vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 76.0 | 76.7
vc1dsp.vc1_inv_trans_8x8_dc_c: 255.0 | 254.7
vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5 | 93.0
> The code below uses fractional multipliers, so I infer that the
benchmarked
> code was significantly different, and the measurements are not really
worth the
> bother.
>
> I know that supply is a problem at the moment, but I if you are going to
keep
> this up, I would hope that ISCAS can get you access to an RVV 1.0 board.
Using mf2 only requires changing the first vset and the last vset in each
function to mf2.
I guess they would achieve similar effects on both c910 and c908?
example in 8x8
```
- vsetivli zero, 8, e64, m4, ta, ma
+ vsetivli zero, 8, e8, mf2, ta, ma
- vsetvli zero, zero, e64, m4, ta, ma
+ vsetivli zero, 8, e8, mf2, ta, ma
```
And ISCAS seems to have no announcement about getting an RVV 1.0 board. I
plan to ask about it from time to time.
Rémi Denis-Courmont <remi at remlab.net> 于2023年12月4日周一 01:17写道：
> Le sunnuntaina 3. joulukuuta 2023, 16.40.08 EET flow gg a écrit :
> > c910
> > vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0
> > vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0
> > vc1dsp.vc1_inv_trans_4x8_dc_c: 150.2
> > vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5
> > vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0
> > vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 75.7
> > vc1dsp.vc1_inv_trans_8x8_dc_c: 254.7
> > vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5
>
> The code below uses fractional multipliers, so I infer that the
> benchmarked
> code was significantly different, and the measurements are not really
> worth the
> bother.
>
> I know that supply is a problem at the moment, but I if you are going to
> keep
> this up, I would hope that ISCAS can get you access to an RVV 1.0 board.
>
> In-line...
>
> > diff --git a/libavcodec/riscv/vc1dsp_init.c
> b/libavcodec/riscv/vc1dsp_init.c
> > new file mode 100644
> > index 0000000000..88e0434f0e
> > --- /dev/null
> > +++ b/libavcodec/riscv/vc1dsp_init.c
> > @@ -0,0 +1,47 @@
> > +/*
> > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences
> > (ISCAS).
> > + *
> > + * This file is part of FFmpeg.
> > + *
> > + * FFmpeg is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * FFmpeg is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with FFmpeg; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> 02110-1301
> > USA
> > + */
> > +
> > +#include <stdint.h>
> > +
> > +#include "libavutil/attributes.h"
> > +#include "libavutil/cpu.h"
> > +#include "libavutil/riscv/cpu.h"
> > +#include "libavcodec/vc1.h"
> > +
> > +void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +
> > +av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
> > +{
> > +#if HAVE_RVV
> > + int flags = av_get_cpu_flags();
> > +
> > + if (flags & AV_CPU_FLAG_RVV_I64) {
> > + dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv;
> > + dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv;
> > + }
> > + if (flags & AV_CPU_FLAG_RVV_I32) {
> > + dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
> > + dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
> > + }
>
> Probably missing VLENB checks.
>
> > +#endif
> > +}
> > diff --git a/libavcodec/riscv/vc1dsp_rvv.S
> b/libavcodec/riscv/vc1dsp_rvv.S
> > new file mode 100644
> > index 0000000000..8a6b27192a
> > --- /dev/null
> > +++ b/libavcodec/riscv/vc1dsp_rvv.S
> > @@ -0,0 +1,123 @@
> > +/*
> > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences
> > (ISCAS).
> > + *
> > + * This file is part of FFmpeg.
> > + *
> > + * FFmpeg is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * FFmpeg is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with FFmpeg; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> 02110-1301
> > USA
> > + */
> > +
> > +#include "libavutil/riscv/asm.S"
> > +
> > +func ff_vc1_inv_trans_8x8_dc_rvv, zve64x
> > + lh t2, (a2)
> > + li t1, 3
> > + mul t2, t2, t1
>
> You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add
> then shift, and by 17 with shift then add. You don't need multiplications.
>
> > + addi t2, t2, 1
> > + srai t2, t2, 1
> > + mul t2, t2, t1
> > + addi t2, t2, 16
> > + srai t2, t2, 5
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vlse64.v v0, (a0), a1
> > + li t0, 8*8
> > + vsetvli zero, t0, e16, m8, ta, ma
> > + vmv.v.x v8, t2
>
> Do you really need to splat? Can't .vx or .wx be used instead?
>
> > + vsetvli zero, t0, e8, m4, ta, ma
> > + vwaddu.wv v8, v8, v0
> > + vsetvli zero, t0, e16, m8, ta, ma
> > + vmax.vx v8, v8, zero
> > + vsetvli zero, t0, e8, m4, ta, ma
> > + vnclipu.wi v0, v8, 0
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vsse64.v v0, (a0), a1
> > + ret
> > +endfunc
> > +
> > +func ff_vc1_inv_trans_4x8_dc_rvv, zve32x
> > + lh t2, (a2)
> > + li t1, 17
> > + mul t2, t2, t1
> > + addi t2, t2, 4
> > + srai t2, t2, 3
> > + li t1, 12
> > + mul t2, t2, t1
> > + addi t2, t2, 64
> > + srai t2, t2, 7
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vlse32.v v0, (a0), a1
> > + li t0, 4*8
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmv.v.x v4, t2
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vwaddu.wv v4, v4, v0
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmax.vx v4, v4, zero
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vnclipu.wi v0, v4, 0
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vsse32.v v0, (a0), a1
> > + ret
> > +endfunc
> > +
> > +func ff_vc1_inv_trans_8x4_dc_rvv, zve64x
> > + lh t2, (a2)
> > + li t1, 3
> > + mul t2, t2, t1
> > + addi t2, t2, 1
> > + srai t2, t2, 1
> > + li t1, 17
> > + mul t2, t2, t1
> > + addi t2, t2, 64
> > + srai t2, t2, 7
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vlse64.v v0, (a0), a1
> > + li t0, 8*4
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmv.v.x v4, t2
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vwaddu.wv v4, v4, v0
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmax.vx v4, v4, zero
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vnclipu.wi v0, v4, 0
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vsse64.v v0, (a0), a1
> > + ret
> > +endfunc
> > +
> > +func ff_vc1_inv_trans_4x4_dc_rvv, zve32x
> > + lh t2, (a2)
> > + li t1, 17
> > + mul t2, t2, t1
> > + addi t2, t2, 4
> > + srai t2, t2, 3
> > + mul t2, t2, t1
> > + addi t2, t2, 64
> > + srai t2, t2, 7
> > + vsetivli zero, 4, e8, mf2, ta, ma
> > + vlse32.v v0, (a0), a1
> > + li t0, 4*4
> > + vsetvli zero, t0, e16, m2, ta, ma
> > + vmv.v.x v2, t2
> > + vsetvli zero, t0, e8, m1, ta, ma
> > + vwaddu.wv v2, v2, v0
> > + vsetvli zero, t0, e16, m2, ta, ma
> > + vmax.vx v2, v2, zero
> > + vsetvli zero, t0, e8, m1, ta, ma
> > + vnclipu.wi v0, v2, 0
> > + vsetivli zero, 4, e8, mf2, ta, ma
> > + vsse32.v v0, (a0), a1
> > + ret
> > +endfunc
> > diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c
> > index 62c8eb21fa..2caa3c6863 100644
> > --- a/libavcodec/vc1dsp.c
> > +++ b/libavcodec/vc1dsp.c
> > @@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp)
> > ff_vc1dsp_init_arm(dsp);
> > #elif ARCH_PPC
> > ff_vc1dsp_init_ppc(dsp);
> > +#elif ARCH_RISCV
> > + ff_vc1dsp_init_riscv(dsp);
> > #elif ARCH_X86
> > ff_vc1dsp_init_x86(dsp);
> > #elif ARCH_MIPS
> > diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h
> > index 7ed1776ca7..e3b90d2b62 100644
> > --- a/libavcodec/vc1dsp.h
> > +++ b/libavcodec/vc1dsp.h
> > @@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c);
> > void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_arm(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_ppc(VC1DSPContext *c);
> > +void ff_vc1dsp_init_riscv(VC1DSPContext *c);
> > void ff_vc1dsp_init_x86(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_mips(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp);
>
> --
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>
>
>
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