[FFmpeg-devel] [PATCH] Fix the tail handling in R-V V sad

[flow gg]

> That makes zero sense. The logical multiplier does not accommodate larger
> vector lengths than 256 bits as things stand, and in the extreme, you can
> always have vector lengths to large that even the smallest valid
multiplier is
> "too" large.

Yes, I didn't consider vlen > 256. What do you think about adding a
parameter for it?

<uk7b-at-foxmail.com at ffmpeg.org> 于2024年12月23日周一 23:02写道：

> From: sunyuechi <sunyuechi at iscas.ac.cn>
>
> ---
>  libavcodec/riscv/h26x/asm.S    | 36 +++++++++++++++++-----------------
>  libavcodec/riscv/vvc/sad_rvv.S |  2 +-
>  2 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/libavcodec/riscv/h26x/asm.S b/libavcodec/riscv/h26x/asm.S
> index d99690d9a0..0c9ebbdaad 100644
> --- a/libavcodec/riscv/h26x/asm.S
> +++ b/libavcodec/riscv/h26x/asm.S
> @@ -20,46 +20,46 @@
>
>  #include "libavutil/riscv/asm.S"
>
> -.macro vsetvlstatic w, vlen, en, mn1, mn2, mn3, mn4, mn5, mn6
> +.macro vsetvlstatic w, vlen, en, mn1, mn2, mn3, mn4, mn5, mn6, vta=ta
>          .if \w == 2 && \vlen == 128
> -                vsetivli        zero, \w, \en, \mn1, ta, ma
> +                vsetivli        zero, \w, \en, \mn1, \vta, ma
>          .elseif \w <= 4 && \vlen == 128
> -                vsetivli        zero, \w, \en, \mn2, ta, ma
> +                vsetivli        zero, \w, \en, \mn2, \vta, ma
>          .elseif \w <= 8 && \vlen == 128
> -                vsetivli        zero, \w, \en, \mn3, ta, ma
> +                vsetivli        zero, \w, \en, \mn3, \vta, ma
>          .elseif \w <= 16 && \vlen == 128
> -                vsetivli        zero, \w, \en, \mn4, ta, ma
> +                vsetivli        zero, \w, \en, \mn4, \vta, ma
>          .elseif \w <= 32 && \vlen == 128
>                  li              t0, \w
> -                vsetvli         zero, t0, \en, \mn5, ta, ma
> +                vsetvli         zero, t0, \en, \mn5, \vta, ma
>          .elseif \w <= 4 && \vlen == 256
> -                vsetivli        zero, \w, \en, \mn1, ta, ma
> +                vsetivli        zero, \w, \en, \mn1, \vta, ma
>          .elseif \w <= 8 && \vlen == 256
> -                vsetivli        zero, \w, \en, \mn2, ta, ma
> +                vsetivli        zero, \w, \en, \mn2, \vta, ma
>          .elseif \w <= 16 && \vlen == 256
> -                vsetivli        zero, \w, \en, \mn3, ta, ma
> +                vsetivli        zero, \w, \en, \mn3, \vta, ma
>          .elseif \w <= 32 && \vlen == 256
>                  li              t0, \w
> -                vsetvli         zero, t0, \en, \mn4, ta, ma
> +                vsetvli         zero, t0, \en, \mn4, \vta, ma
>          .elseif \w <= 64 && \vlen == 256
>                  li              t0, \w
> -                vsetvli         zero, t0, \en, \mn5, ta, ma
> +                vsetvli         zero, t0, \en, \mn5, \vta, ma
>          .else
>                  li              t0, \w
> -                vsetvli         zero, t0, \en, \mn6, ta, ma
> +                vsetvli         zero, t0, \en, \mn6, \vta, ma
>          .endif
>  .endm
>
> -.macro vsetvlstatic8 w, vlen
> -        vsetvlstatic \w, \vlen, e8, mf8, mf4, mf2, m1, m2, m4
> +.macro vsetvlstatic8 w, vlen, vta
> +        vsetvlstatic \w, \vlen, e8, mf8, mf4, mf2, m1, m2, m4, \vta
>  .endm
>
> -.macro vsetvlstatic16 w, vlen
> -        vsetvlstatic \w, \vlen, e16, mf4, mf2, m1, m2, m4, m8
> +.macro vsetvlstatic16 w, vlen, vta
> +        vsetvlstatic \w, \vlen, e16, mf4, mf2, m1, m2, m4, m8, \vta
>  .endm
>
> -.macro vsetvlstatic32 w, vlen
> -        vsetvlstatic \w, \vlen, e32, mf2, m1, m2, m4, m8, m8
> +.macro vsetvlstatic32 w, vlen, vta
> +        vsetvlstatic \w, \vlen, e32, mf2, m1, m2, m4, m8, m8, \vta
>  .endm
>
>  .macro POW2_JMP_TABLE id, vlen
> diff --git a/libavcodec/riscv/vvc/sad_rvv.S
> b/libavcodec/riscv/vvc/sad_rvv.S
> index 341167be1f..bb613cc340 100644
> --- a/libavcodec/riscv/vvc/sad_rvv.S
> +++ b/libavcodec/riscv/vvc/sad_rvv.S
> @@ -37,7 +37,7 @@ SADVSET\vlen\w:
>          vsetvlstatic32    \w, \vlen
>          vmv.v.i           v0, 0
>          vmv.s.x           v24, zero
> -        vsetvlstatic16    \w, \vlen
> +        vsetvlstatic16    \w, \vlen, tu
>  SAD\vlen\w:
>          addi              a5, a5, -2
>          vle16.v           v8, (a0)
> --
> 2.47.1
>
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