[FFmpeg-devel] [PATCH] lavc/flacdsp: do not assume maximum R-V VL

[Rémi Denis-Courmont]

This loop correctly assumes that VLMAX=16 (4x128-bit vectors
with 32-bit elements) and 32 >= pred_order > 16. We need to alternate
between VL=16 and VL=t2=pred_order-16 elements to add up to pred_order.

The current code requests AVL=a2=pred_order elements. In QEMU and on
thte K230 hardware, this sets VL=16 as we need. But the specification
merely guarantees that we get: ceil(AVL / 2) <= VL <= VLMAX. For
instance, if pred_order equals 27, we could end up with VL=14 or VL=15
instead of VL=16. So instead, request literally VLMAX=16.
---
 libavcodec/riscv/flacdsp_rvv.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libavcodec/riscv/flacdsp_rvv.S b/libavcodec/riscv/flacdsp_rvv.S
index 60c9d03344..da8756a2f9 100644
--- a/libavcodec/riscv/flacdsp_rvv.S
+++ b/libavcodec/riscv/flacdsp_rvv.S
@@ -56,11 +56,11 @@ func ff_flac_lpc32_rvv, zve64x
         vle32.v v16, (a0)
         sh2add  a0, a2, a0
 1:
-        vsetvli zero, a2, e32, m4, ta, ma
+        vsetvli t1, zero, e32, m4, ta, ma
         vwmul.vv v24, v8, v16
         vsetvli zero, t2, e32, m4, tu, ma
         vwmacc.vv v24, v12, v20
-        vsetvli zero, a2, e64, m8, ta, ma
+        vsetvli t1, zero, e64, m8, ta, ma
         vredsum.vs v24, v24, v0
         lw      t0, (a0)
         addi    a4, a4, -1
-- 
2.45.1