[MPlayer-cvslog] r24536 - trunk/vidix/nvidia_vid.c

[Sascha Sommer]

Hi,

On Monday 17 September 2007 14:37, Benjamin Zores wrote:
> On 9/17/07, Sascha Sommer <saschasommer at freenet.de> wrote:
> > Hi,
> >
> > On Saturday 15 September 2007 20:42, ben wrote:
> > > Author: ben
> > > Date: Sat Sep 15 20:42:26 2007
> > > New Revision: 24536
> > >
> > > Log:
> > > fix screen width and height calculation on nvidia vidix (patch by
> > > Guillaume Lecerf (fox at geexbox dot org)
> > >
> > > Modified:
> > >    trunk/vidix/nvidia_vid.c
> > >
> > > Modified: trunk/vidix/nvidia_vid.c
> > > =======================================================================
> > >==== === --- trunk/vidix/nvidia_vid.c       (original)
> > > +++ trunk/vidix/nvidia_vid.c  Sat Sep 15 20:42:26 2007
> > > @@ -658,7 +658,11 @@ static void nv_getscreenproperties(struc
> > >    else info->depth = 0x04 << bpp;
> > >    /*get screen width*/
> > >    VID_WR08(info->chip.PCIO, 0x03D4, 0x1);
> > > -  info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8;
> > > +  info->screen_x = VID_RD08(info->chip.PCIO, 0x3D5);
> > > +  /* NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 */
> > > +  VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D);
> > > +  info->screen_x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x02) << 7;
> > > +  info->screen_x = (info->screen_x + 1) << 3;
> > >    /*get screen height*/
> > >    /* get first 8 bits in VT_DISPLAY_END*/
> > >    VID_WR08(info->chip.PCIO, 0x03D4, 0x12);
> > > @@ -669,6 +673,12 @@ static void nv_getscreenproperties(struc
> > >    /* and the 10th in CRTC_OVERFLOW*/
> > >    info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3;
> > >    ++info->screen_y;
> > > +  /* NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 */
> > > +  VID_WR08(info->chip.PCIO,0x03D4,0x25);
> > > +  info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<9;
> > > +  /* NV_PCRTC_???_VERT_DISPLAY_END_11 */
> > > +  VID_WR08(info->chip.PCIO,0x03D4,0x41);
> > > +  info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x04)<<9;
> > >
> > >    /* NV_PCRTC_OFFSET */
> > >    VID_WR08 (info->chip.PCIO, 0x3D4, 0x13);
> >
> > This breaks the screensize detection on nv03 and maybe other cards, too.
> >
> > [nvidia_vid] Found chip: Riva128
> > [nvidia_vid] arch 3 register base 0xb6723000
> > [nvidia_vid] detected memory size 8 MB
> > [nvidia_vid] MTRR set up
> > [nvidia_vid] video mode: 1280x3072 at 15
> >
> >
> > Should have been 1280x1024.
>
> So it was correctly detected before ?
> Seems ok on FX5500.
> I'll either revert or provide a fix.
>

Yes. It was at least correct for NV03, NV04 and NV15 (arch 10) as far as I can 
tell.

Regards

Sascha