[MPlayer-cvslog] r37855 - trunk/cpuinfo.c

[zuxy]

Author: zuxy
Date: Sat Apr 16 01:58:16 2016
New Revision: 37855

Log:
Support CPUID Func 7, Leaf 0 for additional flags like avx2

Modified:
   trunk/cpuinfo.c

Modified: trunk/cpuinfo.c
==============================================================================
--- trunk/cpuinfo.c	Sat Apr 16 01:36:28 2016	(r37854)
+++ trunk/cpuinfo.c	Sat Apr 16 01:58:16 2016	(r37855)
@@ -50,7 +50,7 @@ typedef struct cpuid_regs {
 } cpuid_regs_t;
 
 static cpuid_regs_t
-cpuid(int func) {
+cpuid(int func, int sub) {
     cpuid_regs_t regs;
 #define CPUID   ".byte 0x0f, 0xa2; "
 #ifdef __x86_64__
@@ -65,7 +65,7 @@ cpuid(int func) {
             "xchg %%esi, %%ebx\n\t"
 #endif
             : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx)
-            : "0" (func));
+            : "0" (func), "2" (sub));
     return regs;
 }
 
@@ -118,11 +118,12 @@ main(void)
     unsigned max_ext_cpuid;
     unsigned int amd_flags;
     unsigned int amd_flags2;
+    unsigned int ext_flags;
     const char *model_name = NULL;
     int i;
     char processor_name[49];
 
-    regs = cpuid(0);
+    regs = cpuid(0, 0);
     max_cpuid = regs.eax;
     /* printf("%d CPUID function codes\n", max_cpuid+1); */
 
@@ -132,16 +133,16 @@ main(void)
     idstr[12] = 0;
     printf("vendor_id\t: %s\n", idstr);
 
-    regs_ext = cpuid((1<<31) + 0);
+    regs_ext = cpuid((1<<31) + 0, 0);
     max_ext_cpuid = regs_ext.eax;
     if (max_ext_cpuid >= (1<<31) + 1) {
-        regs_ext = cpuid((1<<31) + 1);
+        regs_ext = cpuid((1<<31) + 1, 0);
         amd_flags = regs_ext.edx;
         amd_flags2 = regs_ext.ecx;
 
         if (max_ext_cpuid >= (1<<31) + 4) {
             for (i = 2; i <= 4; i++) {
-                regs_ext = cpuid((1<<31) + i);
+                regs_ext = cpuid((1<<31) + i, 0);
                 store32(processor_name + (i-2)*16, regs_ext.eax);
                 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx);
                 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx);
@@ -158,6 +159,13 @@ main(void)
         amd_flags2 = 0;
     }
 
+    if (max_cpuid >= 7) {
+        regs_ext = cpuid(7, 0);
+        ext_flags = regs_ext.ebx;
+    } else {
+        ext_flags = 0;
+    }
+
     if (max_cpuid >= 1) {
         static struct {
             int bit;
@@ -280,9 +288,43 @@ main(void)
             CPUID_FEATURE_DEF(29, "mwaitx", "MONITORX/MWAITX"),
             { -1 }
         };
+        static struct {
+            int bit;
+            char *desc;
+        } cap_ext[] = {
+            CPUID_FEATURE_DEF(0, "fsgsbase", "{RD/WR}{FS/GS}BASE instructions"),
+            CPUID_FEATURE_DEF(1, "tsc_adjust", "TSC adjustment MSR 0x3b"),
+            CPUID_FEATURE_DEF(2, "sgx", "Software Guard Extensions"),
+            CPUID_FEATURE_DEF(3, "bmi1", "1st group bit manipulation"),
+            CPUID_FEATURE_DEF(4, "hle", "Hardware Lock Elision"),
+            CPUID_FEATURE_DEF(5, "avx2", "AVX2 instructions"),
+            CPUID_FEATURE_DEF(7, "smep", "Supervisor mode execution protection"),
+            CPUID_FEATURE_DEF(8, "bmi2", "2nd group bit manipulation"),
+            CPUID_FEATURE_DEF(9, "erms", "Enhanced REP MOVSB/STOSB"),
+            CPUID_FEATURE_DEF(10, "invpcid", "Invalidate processor context ID"),
+            CPUID_FEATURE_DEF(11, "rtm", "Restricted Transactional Memory"),
+            CPUID_FEATURE_DEF(12, "cqm", "Cache QoS Monitoring"),
+            CPUID_FEATURE_DEF(14, "mpx", "Memory Protection Extension"),
+            CPUID_FEATURE_DEF(16, "avx512f", "AVX-512 Foundation"),
+            CPUID_FEATURE_DEF(17, "avx512dq", "AVX-512 Double/Quad granular"),
+            CPUID_FEATURE_DEF(18, "rdseed", "The RDSEED instruction"),
+            CPUID_FEATURE_DEF(19, "adx", "ADCX and ADOX instructions"),
+            CPUID_FEATURE_DEF(20, "smap", "Supservisor mode access prevention"),
+            CPUID_FEATURE_DEF(22, "pcommit", "PCOMMIT instruction"),
+            CPUID_FEATURE_DEF(23, "clflushopt", "CLFLUSHOPT instruction"),
+            CPUID_FEATURE_DEF(24, "clwb", "CLWB instruction"),
+            CPUID_FEATURE_DEF(26, "avx512pf", "AVX-512 Prefetch"),
+            CPUID_FEATURE_DEF(27, "avx512er", "AVX-512 Exponential and Reciprocal"),
+            CPUID_FEATURE_DEF(28, "avx512cd", "AVX-512 Conflict Detection"),
+            CPUID_FEATURE_DEF(29, "sha_ni", "SHA extensions"),
+            CPUID_FEATURE_DEF(30, "avx512bw", "AVX-512 Byte/Word granular"),
+            CPUID_FEATURE_DEF(31, "avx512vl", "AVX-512 128/256 Vector Length"),
+            { -1 }
+        };
+
         unsigned int family, model, stepping;
 
-        regs = cpuid(1);
+        regs = cpuid(1, 0);
         family = (regs.eax >> 8) & 0xf;
         model = (regs.eax >> 4) & 0xf;
         stepping = regs.eax & 0xf;
@@ -343,6 +385,11 @@ main(void)
                 printf(" %s", cap_amd2[i].desc);
             }
         }
+        for (i = 0; cap_ext[i].bit >= 0; i++) {
+            if (ext_flags & (1 << cap_ext[i].bit)) {
+                printf(" %s", cap_ext[i].desc);
+            }
+        }
         printf("\n");
 
         if (regs.edx & (1 << 4)) {