[MPlayer-dev-eng] "lockless" cache2 looks buggy

[Rich Felker]

On Fri, Aug 25, 2006 at 09:30:28PM -0700, Loren Merritt wrote:
> On Fri, 25 Aug 2006, Rich Felker wrote:
> >On Fri, Aug 25, 2006 at 10:46:58PM +0200, Denis Vlasenko wrote:
> >>
> >>These updates are not atomic on 32-bit architectures (i386).
> >>Therefore caching thread can update lower half of a value, then it
> >>may get rescheduled with CPU given to main thread, which then
> >>will use bogus value of half-updated variable.
> >>
> >>If you don't believe me, add asm() statements as shown below:
> >>
> >>asm("#1");
> >>  s->max_filepos+=len;
> >>asm("#1");
> >
> >Maybe this works:
> >
> >union { off_t o; double d; } foo = { s->max_filepos + len };
> >*(double *)&s->max_filepos = foo.d;
> >
> >?? I'm sure there are better implementations of the same idea.
> 
> That compiles to exactly the same non-atomic stores if optimization is 
> enabled. I don't know any way other than inline asm to force gcc to 
> generate an atomic store.

Maybe *(double *)&s->max_filepos = foo.d + 0.0;
i.e. force nonsense float arithmetic on it so the store will be fpu
register to memory rather than memory to memory. The compiler cannot
optimize it away because it might generate fpu exceptions.

Rich